Espressif Systems /ESP32-S2 /PMS /PRO_DRAM0_1

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Interpret as PRO_DRAM0_1

Description

DBUS permission control register 1.

Fields

PRO_DRAM0_SRAM_0_R	Setting to 1 grants DBUS0 permission to read SRAM Block 0.
PRO_DRAM0_SRAM_0_W	Setting to 1 grants DBUS0 permission to write SRAM Block 0.
PRO_DRAM0_SRAM_1_R	Setting to 1 grants DBUS0 permission to read SRAM Block 1.
PRO_DRAM0_SRAM_1_W	Setting to 1 grants DBUS0 permission to write SRAM Block 1.
PRO_DRAM0_SRAM_2_R	Setting to 1 grants DBUS0 permission to read SRAM Block 2.
PRO_DRAM0_SRAM_2_W	Setting to 1 grants DBUS0 permission to write SRAM Block 2.
PRO_DRAM0_SRAM_3_R	Setting to 1 grants DBUS0 permission to read SRAM Block 3.
PRO_DRAM0_SRAM_3_W	Setting to 1 grants DBUS0 permission to write SRAM Block 3.
PRO_DRAM0_SRAM_4_SPLTADDR	Configure the split address of SRAM Block 4-21 for DBUS0 access.
PRO_DRAM0_SRAM_4_L_R	Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 low address region.
PRO_DRAM0_SRAM_4_L_W	Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 low address region.
PRO_DRAM0_SRAM_4_H_R	Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 high address region.
PRO_DRAM0_SRAM_4_H_W	Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 high address region.

Links

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